The Silicon Design group is a diverse team of world class silicon engineers. We have 100+ years of cumulative hands-on experience in architecture, logic design, verification, physical design, emulation and firmware. We use the latest silicon technologies and processes to help our clients create well-designed solutions to highly complex challenges. We are designing and developing next-generation, high performance SoCs, supporting our clients in their drive to deliver their product vision to their users. We are involved in all aspects of chip design from definition and architecture through to verification and signoff. Accenture engineers are true “Silicon to SW” Partners, allowing a new breed of companies in the semiconductor ecosystem to innovate in an unparalleled time to market.
An experienced ASIC Design Verification Engineer able to provide design verification services for complex multi-CPU/DSP SoC on the most advance technology notes.
Develop test plans, tests and verification infrastructure for verifying DSP blocks.
Build verification environment using SV/UVM methodology
Build reusable bus functional models, monitors, checkers and scoreboards
Drive coverage driven verification closure
Work with architects, designers and post-silicon teams.
Working with cross functional teams (DV/Arch/Design/FW) to identify coverage scope
Here's what you need:
A minimum of two years of experience with RTL Design and Verification
Bachelor’s Degree or equivalent (12 years) work experience (If an, Associate’s Degree with 6 years of work experience)
Bonus points if:
Knowledge of System Verilog UVM and vertical testbench integration
Experience with low level SW debug - disasm, Tarmac, trace
Experience with RISC-V architecture
Experience with coresight architecture
Experience with embedded SW low level concepts and debug - Tarmac, ROM, RAM,
linkers, elf, disasm, code sections, cache, security
Experience with coverage merging across simulation and emulation
Experience with Power Aware and Gate Level Netlist in Emulation
Experience with development of fully automated flows
Experience with Gate Level Simulations
Compensation at Accenture varies depending on a wide array of factors, which may include but are not limited to the specific office location, role, skill set, and level of experience. As required by local law, Accenture provides a reasonable range of compensation for roles that may be hired in Albany County, NY, California, Colorado, New York City or Washington as set forth below.
Information on benefits is here.
Role Location: Range of Starting Pay for role
California: $63,200 -$220,400
Colorado: $63,200 - $190,400
New York - Albany: $58,500 to $176,300
New York City: $73,100- $220,400
Washington: $67,300- $202,700
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