Emulation and Prototyping Engineer

We Are:

The Silicon Design group is a diverse team of world class silicon engineers. We have 100+ years of cumulative hands-on experience in architecture, logic design, verification, physical design, emulation and firmware. We use the latest silicon technologies and processes to help our clients create well-designed solutions to highly complex challenges. We are designing and developing next-generation, high performance SoCs, supporting our clients in their drive to deliver their product vision to their users. We are involved in all aspects of chip design from definition and architecture through to verification and signoff. Accenture engineers are true “Silicon to SW” Partners, allowing a new breed of companies in the semiconductor ecosystem to innovate in an unparalleled time to market.

You Are:

An experienced Emulation and Prototyping Engineer

The Work:

• Port ASIC and IP RTL code to prototyping and emulation platforms (Preferred/Required experience: HAPS)

• Build model from released RTL

• Generate loadable image(s) for target prototyping and emulation platform

• Run sanity tests to qualify release of the image(s)

• Release the emulation/prototyping images to various teams doing functional validation, firmware development and design verification

• Assist debug of failures with stakeholder by providing instrumented models and captured waveforms extracted from in-circuit debug logic

• Coordinate with EDA and prototyping tools team to validate implementation flows

Here’s what you need:

• A Minimum 3 years of experience in Simulation, Emulation, Prototyping or FPGA design and verification using System Verilog/Verilog/VHDL

• Bachelor’s Degree or equivalent (12 years) work experience (If an, Associate’s Degree with 6 years of work experience)

Bonus points if:

• Good knowledge of SoC design methodologies and technologies, with experience in the complete design validation cycle

• Emulation experience on available platforms, Palladium and Zebu, including compilation, debug, and performance.

• Good knowledge of RTL synthesis, mapping RTL to FPGA-based platforms, Unix/Linux development environments and scripting languages like Tcl, Python, C-shell

• Working knowledge of C/C++ is a plus

• Knowledge of key protocol’s like PCIe, USB, Ethernet, AMBA, UART, DDR, flash memories and their usage in SoC environments is a plus

Compensation at Accenture varies depending on a wide array of factors, which may include but are not limited to the specific office location, role, skill set, and level of experience. As required by local law, Accenture provides a reasonable range of compensation for roles that may be hired in Albany County, NY, California, Colorado, New York City or Washington as set forth below.

Information on benefits is here.

Role Location: Range of Starting Pay for role 

California: $63,200 -$220,400 

Colorado: $63,200 - $190,400

New York - Albany: $58,500 to $176,300

New York City: $73,100- $220,400

Washington: $67,300- $202,700 

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