ASIC Design Engineer - Pixel IP

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As an ASIC Design Engineer in the Pixel IP design team, you will work closely with many multi-functional teams (chip integration, physical design, power, logic design, and verification) to build dedication and low power pixel processing engines. Your expertise in integrating large systems-on-a-chip, low-power design techniques, and front-end implementation will enable the team to deliver high performance and low power pixel processing engines on time. In this front-end design role, your tasks will include: - Being responsible for the integration of large pixel-processing subsystems using SystemVerilog, connecting to high-performance on-chip networks using virtual memory addressing, adding Design-For-Test (DFT) logic, and managing clocks, resets, and power domains. - Writing detailed micro-architectural specifications. - Performing front-end implementation, including logic synthesis, clock & reset domain-crossing checks, static timing analysis, power analysis, logic equivalence checking. - Working with Physical Design teams for physical floorplanning and timing closure. - Collaborating with multi-functional teams to explore solutions that improve performance while minimizing power and area. - Working closely with design verification and formal verification teams to debug and verify functionality and performance.

Minimum Qualifications

• BS and a minimum of 10 years relevant industry experience.

Preferred Qualifications

• Experience in IP/SoC front-end ASIC RTL digital logic design using Verilog and System Verilog.

• Extensive shown experience in ASIC implementation, especially logic synthesis, static timing analysis, logic equivalence checking, and working with physical design teams for floorplanning and timing closure.

• Deep experience with system design methodologies that contain multiple clock domains.

• Practiced in low-power design issues, tools, and methodologies including UPF power intent specification.

• Familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB).

• Industry exposure to and knowledge of ASIC/FPGA design methodology including familiarity with relevant scripting languages (Python, Perl, TCL).

• Tight-knit collaboration skills with excellent written and verbal communication skills.

• Extensive experience working multi-functionally with integration, design, and verification teams to specify, design, and debug digital systems.

Pay & Benefits

At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $175,800 and $312,200, and your base pay will depend on your skills, qualifications, experience, and location.

Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits.

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

More

• Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.