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imary responsibilities will include: - Developing, maintaining, and enhancing CAD applications for logical equivalence. - Supporting frontend design closure , ECO verification, and flow signoff. - Triaging and solving CAD flow problems, and working around EDA tool problems. - Working directly with EDA vendors to resolve tool issues, and identifying enhancements. - Working directly with EDA vendors to architect new tool features and methodologies. - Collaborating with other CAD engineers, including synthesis, DV, analytics, and signoff to build integrated flows. - Participating and engaging with cross functional teams to tackle key logic equivalence challenges. - Using ML and GenAI based solutions to improve CAD applications.
Minimum Qualifications
Experience with ASIC Design EDA Tools, CAD flows, and/or ASIC design methodologies.
Knowledge of Tcl, Python or Perl scripting languages.
Knowledge of Verilog or SystemVerilog coding for hardware design or verification.
Minimum requirement of BS and 3+ years of relevant industry experience.
Preferred Qualifications
Strong proficiency in scripting languages, such as Python, Perl, and TCL
Excellent communication skills, including previous customer support experience
Excellent interpersonal skills, including collaboration, inclusivity, active listening, and a growth mindset.
Expertise in industry standard equivalence checking EDA tools
Expertise in industry standard ASIC synthesis EDA tools
Understanding of frontend digital design methodologies, including simulation, synthesis, RTL linting, low power verification, BIST, DFT, design integration, and frontend signoff.
Experience architecting and implementing CAD flows
Comfort within Linux/Unix environments.
Understanding of software engineering practices (agile, code reviews, unit level testing, regression testing).
Familiarity with current Gen AI research in one of the following areas: RAG, Semantic Search, or Prompt Engineering is a plus
Additional Requirements
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