CAD Engineer - PDV

rious technology nodes and tool sets. Working alongside the CAD team, you will be collaborating with the custom digital/analog/mixed-signal design, physical design (PD) and chip integration teams. With good understanding of design rule checks (DRC) and layout versus schematic (LVS) runsets, you will develop rule decks from scratch and/or modify existing ones.

Description

• Develop, improve and maintain various aspects of physical verification flow and methodology - Coordinate the effort of validating flows, improving for custom checks and data generation - Work with the design and PD teams to facilitate the chip design process - Code custom PDV rule decks such as Electrical rule checks (ERC) and Programmable ERCs - Collaborate with tool vendors and foundries for PDK performance enhancements

Minimum Qualifications

• Previous industry experience in Silicon chip design flows

• Tapeout support and IP/SOC level PDV debug experience in various technology nodes

• Scripting skills in programming languages such as Python, Perl, Tcl, Shell, Makefile or C

• Experience with flow automation and development in advanced nodes

• Minimum requirement of BS and 10+ years of relevant industry experience

Preferred Qualifications

• Knowledge in Calibre/ICV runset coding for DRC/LVS/ERC/MFILL

• Rule coding in PERC is a plus

• Knowledge of parasitic extraction, SKILL coding, and PnR tools is a plus

Additional Requirements

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