#200562874-4
As a RTL Engineer, you will own or participate in the following: Microarchitecture development and specification - from early high-level architectural exploration through micro architectural research and arriving at a detailed specification RTL ownership - development, assessment and refinement of RTL design to target power, performance, area and timing goals Validation - support test bench development and simulation for functional and performance verification Performance exploration and correlation - explore high performance strategies and validate that the RTL design meets targeted performance Design delivery - work with multifunctional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability, and power
Minimum Qualifications
5+ years of relevant industry experience
Thorough knowledge of microprocessor architecture including expertise in one or more of the following areas: instruction fetch and decode, branch prediction, instruction scheduling and register renaming, out-of-order execution, integer and floating point execution, load/store execution, cache and memory subsystems
Knowledge of Verilog and/or VHDL. Experience with simulators and waveform debugging tools
Knowledge of logic design principles along with timing and power implications
Understanding of low power microarchitecture techniques
Understanding of high performance techniques and trade-offs in a CPU microarchitecture
Experience in C or C++ programming
Experience using an interpretive language such as Perl or Python
Preferred Qualifications