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wn or participate in the following: • Work extensively with Micro-architects to define memory subsystem, perform feasibility, make area, frequency, performance, power trade-offs and design and balance the pipeline stages. • Drive RTL-to-GDS flow through synthesis and place-and-route targeting ambitious targets for power, performance, and area. • Design delivery. Work with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability, and power.
Minimum Qualifications
Minimum BS and 10+ years of relevant industry experience
Familiarity with high-performance microprocessor architecture
Knowledge of logic design principles along with timing and power implications
Deep knowledge of CPU microarchitecture including common critical loops for timing and understanding of low power microarchitecture and implementation techniques for CPUs
Deep understanding of power, performance and area tradeoffs
Experience using synthesis & place-route tools
Experience with scripting in Perl or TCL
Preferred Qualifications
Understanding of static timing and critical path closure techniques
Have design experience in deep sub-micron technologies and basic device physics
Additional Requirements
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