#200577922-2
g the boundaries of innovation in the areas of branch prediction, code/data prefetchers, novel prediction schemes to improve latency and optimization of CPU pipelines. With others you will seek out areas for improvement while collecting data and measurements that either confirm the idea or rule it out. You will collaborate with experienced CPU designers in micro-architecture and RTL to assess the feasibility of ideas through modeling and refine those ideas to make them implementable. The role requires the analysis of specific single-threaded and multi-threaded workloads across existing and new product categories to identify bottlenecks and opportunities for improvement. We collaborate as a larger CPU architecture and performance team to maintain and improve the simulation environment to enable data driven decisions and look for ways to boost the productivity of the entire team.
Minimum Qualifications
BS degree
Knowledge of CPU architecture and micro-architecture
Ability to combine micro-architecture knowledge and performance bottleneck analysis on relevant workloads to conceive novel performance ideas
Experience working with design and implementation teams to iterate on ideas to solve timing and power efficiency challenges and fit them into system constraints
Familiarity with performance and/or power simulation environments and ability to take ideas from concept to C/C++ simulator implementation
Experience in scripting languages such as Perl or Python
Preferred Qualifications
15+ years of relevant industry experience.
MS or PhD in Electrical or Computer Engineering or Computer Science
Understanding of common data structures and algorithms
Knowledge in software design patterns
Familiarity with SIMD and vector architectures
Knowledge of OS internals and compiler technologies
Comfortable in an environment of uncertainty and able to work through ambiguities
Communication, influence and negotiation skills
Additional Requirements
More