#200572212-3
irritators on FPGA, and executing parts of functional silicon bringup plans.
Description
In this highly visible and interactive role, your primary responsibilities will be: • Drive end-to-end silicon test plan development and execution across CPU product cycle • Reproduction of silicon failures on FPGA/Emulation • Contribute to design of hardware irritators to validate features on silicon and pre-silicon • FPGA model build and methodology for ECO verification
Minimum Qualifications
Minimum BS and 10+ years of relevant industry experience
Academic understanding of CPU architecture and microarchitecture
C and assembly programming skills
Experience in scripting
Preferred Qualifications
Bachelor of Science or Engineering in Electrical Engineering, Computer Engineering, or Computer Science
Academic or industry experience in hardware and low-level software
Operating system knowledge is a notable plus
Understanding of firmware and device drivers
Experience with FPGA model design and optimization
Experience with board level debug is a plus
Industry experience with silicon test plan development and execution
Ability to work with multiple teams in delivering a solution
Additional Requirements
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