DDR Design Engineer

ital designs. You will be responsible for writing detailed design specification and test plans in close collaboration with architecture, circuit designers and verification engineers. You will provide high-quality RTL description, including assertions, for the design. Use formal tools and static checkers to guarantee RTL quality. You will also support design verification to insure bug-free first silicon. Responsibilities will include driving functional and code coverage as well as timing closure for your designs and supporting silicon bring-up, performance and power characterization.

Preferred Qualifications

RTL design using Verilog or SystemVerilog, assertion writing.

Design of state machines, data paths, arbitration and clock domain crossing logic.

Logic synthesis, timing constraints.

Exposure to Design For Test, understanding of scan concept and writing DFT friendly RTL.

Unified Power Format for simulation, synthesis and electrical rule checking Equivalence checking.

Prior experience in DDR PHY design and mixed-signal environment is a plus.

Minimum Qualifications

BS degree in technical discipline with minimum 10 years of relevant experience.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant .