Early Careers SOC Physical Design Engineer

Apple

3.7

(120)

Munich, Germany

Why you should apply for a job to Apple:

  • 66% say women are treated fairly and equally to men
  • 66% say the CEO supports gender diversity
  • Ratings are based on anonymous reviews by Fairygodboss members.
  • Company commitment that women earn the same as men performing similar work includes no salary history disclosure policy.
  • Apple University creates classes, seminars, and tools to help employees understand Apple’s culture, organization, and values.
  • Whether you donate time or money, Apple will match charitable contributions up to $10,000 a year.
  • #200581577_EN-1

    Position summary

    n Physical Design? Do you have strong track record with recent successful tape-outs in deep sub-micron technology? As SoC Digital Physical Design Engineer, you will take part in the large scale SoC physical design cycle from netlist to tape-out, including full flow of back-end implementation and verification always meeting schedule and design goals. Are you ready to join some of the world's leading engineers, and help us deliver the next generation of ground-breaking Apple products? Join Us!

    Description

    • As a member of our Physical Design team in this highly transparent role, you will directly own implementation of design partition(s) (netlist to delivery of our final GDS) for a highly complex SoC using brand-new process technology - You are going to own block level PnR, floor-planning, clock and power distribution - You will get involved with static timing closure with commercial tools - You will do power and noise analysis (EM / IR-Drop / Xtalk) as well as layout verification (DRC / LVS) - You will be developing and validating dedication low power clock network guidelines - With phenomenal focus you will resolve design and flow issues related to physical design, and identify potential solutions whilst driving execution - You know what documentation should look like, and will help with guidelines and specs

    Minimum Qualifications

    • You hold a MSEE or equivalent strong experience.

    • English language fluency (written and verbal).

    • We will be counting on your expertise and hands on experience with one of the Place & Route ('PnR') tools available today (Synopsys / Cadence), and having understanding of their capabilities and underlying algorithms.

    • You are familiar with hierarchical design approach, top-down design, and timing and physical convergence.

    • You are demonstrating in-depth understanding of static-timing analysis, extensive know-how in clock/power distribution and analysis, as well as RC extraction and correlation.

    • You have experience with SoC practices such as multiple voltage and clock domains, integration of mixed-signal IPs and I/O integration.

    • You can do scripting and programming using several of the following: Perl, TCL and Make.

    • Your communication skills are excellent, and like the rest of us here at Apple you love working in open and multi-cultural environment.

    Preferred Qualifications

    • We expect experience with large SoC designs (>20M gates) with frequencies in excess of 1GHZ and beyond.
    • If you also have working knowledge in Verilog, that is a huge plus for us.

    Why you should apply for a job to Apple:

  • 66% say women are treated fairly and equally to men
  • 66% say the CEO supports gender diversity
  • Ratings are based on anonymous reviews by Fairygodboss members.
  • Company commitment that women earn the same as men performing similar work includes no salary history disclosure policy.
  • Apple University creates classes, seminars, and tools to help employees understand Apple’s culture, organization, and values.
  • Whether you donate time or money, Apple will match charitable contributions up to $10,000 a year.