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tions and close collaboration with Analog and Digital Design engineers.
Description
Definition and design of Self-checking verification environments for multi-layer systems using the SystemVerilog UVM library. The responsibility spans from concept discussions, verification strategy definition and execution of the verification tasks to ensure bug-free tape-outs. The AMS DV engineer goes beyond standard verification techniques and include: - performance-based analysis - power related analysis and scenario design for early power estimation - deliveries of tests for design and test engineering teams - gate-level verification (power and timing) - lab bring-up support A significant part of the AMS DV team focuses on research and innovations to improve verification techniques and tools for mixed-signal systems in order to increase efficiency and quality. Looking forward and establishing cutting edge concepts and methods to support them are part of the AMS DV team's DNA.
Minimum Qualifications
Knowledge of System Verilog test-bench language and UVM (Universal Verification Methodology)
Hands-on experience with constrained random verification environments
Basic design background in support of verification results analysis
Knowledge of Object Oriented Programming (OOP)
Proficiency in English language is required
Preferred Qualifications