#200576901-2
eople every day.
Description
The successful candidate will work closely with the RTL and PD (physical design) teams and be responsible for synthesis, analysis, and optimization of the delivered IP. For this role, use and develop advanced techniques spanning RTL/Synthesis/PNR to meet challenging timing, power and area targets while also working with our partners in STA and DFT to achieve successful first silicon. Through this collaboration, you will deliver the best-in-class GPU's for the best consumer products. If you're ready to help chart the future of Apple Silicon, we'd love to talk to you.
Minimum Qualifications
Experience driving block level synthesis and optimizations
Experience with RTL design improvement for optimal Area, Timing Power
Experience debugging complex logic equivalence issues and in netlist checks to validate functionality and netlist quality
Experience implementing ECOs for functionality and timing
Experience with one or more of: reset domain, multi-clock domain, multi-power domain (UPF), linting tools across RTL and Gate-Level
Scripting experience in ASIC flows - python, tcl, Perl, Data manipulation
BS + 10 years of relevant experience
Preferred Qualifications
Collaboration with Physical Design and Timing Analysis teams on physical concepts (floor-planning, placement, congestion, and timing constraints)
Demonstrated ability to solve complex problems across multiple technical domains
Ability to analyze architectural critical paths and drive multi-block closure across RTL Design and Physical Design teams
Develop and Drive adoption of innovative methodologies across projects and teams
Familiarity with DFT insertion
Familiarity with simulation, debugging tools and experience of working closely with design verification team
Experience working on GPUs/CPUs is desirable
Additional Requirements
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