#200586889
artitioning, design analysis, qualification, packaging and delivery. - Run logic equivalence checking between designs. - Ensure implementation readiness with RTL lint, custom checks and unit level synthesis. - Develop innovative methods to improve front-end design integration process. - Understand and contribute to specifications for design units. - Collaborate effectively with Architecture, IP, DV, SOC, DFT, IMPL teams spanning multiple sites.
Minimum Qualifications
BS + 3 years of relevant experience.
Experience with Verilog/System Verilog.
Experience with the one of the following scripting languages: Perl/Ruby/Python.
Preferred Qualifications
Knowledge of PPA optimization techniques and implementation flows.
Experience with scalable designs, DFT insertion, LEC, Lint and codeline management.
Ability to debug and solve various design integration issues in a timely manner.
Proficiency in logic design principles.
Proficiency in programming techniques.
Experience with RTL analysis and/or PPA optimization using Invio, LEC and Genus.
Familiarity with GPU/CPU/SIMD Architecture and micro-architecture.
Ability to solve complex problems across multiple technical domains.
Ability to work well in a team and be productive under aggressive schedules.
Additional Requirements
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