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to Stuttgart) has a unique opportunity for a motivated, collaborative, and solution-oriented intern to actively contribute to our chip development.
Description
As an Intern in the PMU Team, you will closely collaborate and engage with members of multi-functional areas including design, verification, and validation teams to learn the fundamentals of building a Power Management IC. This will involve: - Designing/optimising sub-circuits and verifying compliancy to specification - Defining chip-level verification plans to ensure coverage of specified features - Execution of verification plans, analyzing the results and debugging the design - Writing behavioural/functional models for sub-blocks and validating the models against the design
Minimum Qualifications
Enrolled in Bachelors/Masters/PhD program in EE or related field
Eagerness to learn new things and take up new challenges
Fluent English language skills are required
Availability for 6 months or more
Preferred Qualifications