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you or others. You will participate in the design verification and bring-up of such blocks by writing meaningful assertions, debugging code, and otherwise interacting with the design verification team. You will participate in the lab bring-up of those circuits by potentially writing test scripts, analyzing lab data, proposing experiments, etc.
Minimum Qualifications
BS degree in technical discipline with minimum 10 years of relevant experience
Preferred Qualifications
Deep understanding of mixed signal concepts, along with RTL design fundamentals
Deep knowledge of Verilog and System-Verilog
Experience with front-end tools (Verilog simulators, linters, clock-domain crossing checkers)
Working knowledge of synthesis, static timing, DFT is a huge plus
Some working experience with System-Verilog assertions, checkers, and other design verification techniques
Knowledge of SerDes, algorithm developments, scripting languages such as Perl and Python are plusses
Strong communication, collaboration and presentation skills
Additional Requirements
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