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ecified by you or others. You will participate in the design verification and bring-up of such blocks by writing meaningful assertions, debugging code, and otherwise interacting with the design verification team. You will participate in the lab bring-up of those circuits by potentially writing test scripts, analyzing lab data, proposing experiments, etc.
Minimum Qualifications
BS degree in technical discipline with minimum 10 years of relevant experience.
Preferred Qualifications
Deep knowledge of mixed signal concepts
Deep knowledge of RTL design fundamentals
Deep knowledge of Verilog and System-Verilog
Deep knowledge of front-end tools (Verilog simulators, linters, clock-domain crossing checkers)
Working knowledge of synthesis, static timing, DFT is a huge plus
Deep knowledge of System-Verilog assertions, checkers, and other design verification techniques
Deep knowledge of scripting languages. Perl and Python are plusses
Deep knowledge of Algorithm developments
Strong communication and presentation skills SERDES knowledge is a plus
Additional Requirements
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