Senior DFT Engineer

is poised to grow at over 25% per annum.

We are known for our vibrant and dynamic workplace, where personal and professional fulfillment and company success go hand in hand. We take pride in creating exceptional work experiences, encouraging innovation and being involved with our employees, customers and communities. We have been repeatedly recognized by Gartnet/Frost & Sullivan/Zinnov/Deloitte/NASSCOM for variety of our cutting edge work.

Key Responsibilities

• 5 to 10 years of hands-on experience in Scan insertion at block level and/or MBIST insertion at block level

• ATPG and Pattern verification at Block level

• Debug and enhance DFT architecture and setup DFT flow

• Debug iJTAG and IEEE 1500 core wrapper-based architecture

• Pattern diagnosis and debug the ATE pattern failures

• Very good debugging skills

• Boundary Scan implementation

• Create and debug DFT modes timing constraints

• Scripting for flow automation

• Should have worked on below Tools:

Synopsys tools: DFTMAX, TetraMAX, VCS, Verdi and PT

OR Cadence tools: Genus and Modus, NC-SIM/Irun, Sim-Vision, LEC

OR Mentor Graphics tools: Tessent tool chain, TestKompress, Questa

• Ability to work independently on DFT flow enhancement, Full chip/Block level Scan, MBIST. Work closely with DFT lead to solve complex technical issues

• Technically sound & good team player

• Familiarity with ATE will be plus

Worked on at least one Fullchip project is desired

He/She will be using following tools and must posses below experience of tools

• Synopsys Design Compiler

• Synopsys PrimeTime

• Synopsys DFT Compiler

• Synopsys VCS

• Synopsys TetraMAX

• Synopsys Formality

• Mentor ModelSim

• Tessent MemoryBIST

Location:
EG-Cairo, Egypt (Al Emdad & Al Tamween)

Time Type:
Full time

Job Category:
Engineering Services