#R49351
ience in high performance SOC architecture with focus on system-level trade-offs
Development of functional and behavioral (loosly timed)/(cycle-level) models using C++/SystemC/TLM2
Experience in using RTL/UVM System Verilog simulation environments for model validation
Experience in creating workloads for different SoC components at required levels of abstraction
Knowledge of scripting languages (python, perl)
Excellent communication skills and ability to work in a team spread over multiple time-zones
BS/MS degree in Computer Science or Electrical Engineering, or equivalent practical experience(2-3yrs)
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