Design Engineering Architect

nical and project leadership role is responsible for working with IP design teams and silicon solution architects to develop new physical aware IP architectures, collaborating with leading foundries such as TSMC, Samsung, Intel to achieve best Performance/Power/Area (PPA) for Cadence IPs, and guiding Cadence worldwide physical design teams to follow the best design practices and methodologies.
• The position requires 15+ years of experience in design tools, foundry technologies and proven leadership in collaborating and coordinating cross functional teams and external companies to develop industry-leading IPs for advanced technology nodes at world leading semiconducdor foundries.
• Cross functional project management experience with strong communication and inter-personal skills are required.
• Thorough understanding and experience with the full physical design flows including RTL Synthesis, floorplan, P&R, high performance clock-tree synthesis, static Timing analysis and closure, DFT, Low power design techniques, Physical verification.
• Deep knowledge and experience with Cadence tools/flows (Genus, Innovus, Voltus, Tempus, Modus, Conformal-LP, Pegasus).
• Good knowledge with high performance interface PHYs and controllers is highly desirable.

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