#R48471
technology libs.
Job Qualifications:
BS or MS in Electrical Engineering or Computer Science
RTL design experience desired with Verilog/System Verilog
Strong debugging and analytical skills
Digital architecture trade-offs for power, performance and area
Handling of multiple asynchronous clock domains and their crossings (CDC)
RTL lint checks and proper resolution of errors
Working knowledge of UNIX/Linux, shells, programming and scripting
Team player (fluent in English)
Must be legally eligible to work in Poland
Additional Skills/Preferences:
Exposure to modern digital verification flows: functional coverage closure, metric-driven verification, formal verification, etc.
Knowledge of processor-based systems and embedded programming
Semiconductor IP design / FPGA design experience is beneficial
Working knowledge of leading protocols (i.e. PCIe, CXL, AMBA, Ethernet, USB, ...)
Ability to use UVM TB
Check what we can offer you:
Competitive salary package adequate to competencies
Copyrights tax relief procedure implemented in salary calculations
Flexible working hours
Work from office or hybrid
Continuous professional development: trainings and seminars
Possibility to cooperate with people from around the world in an expanding global organization
Employee Stock Purchase Plan, bonuses and stocks
Private medical care
Life insurance
Multisport Plus cards
Social Fund benefits
Recommendation bonuses & internal recognition program
Additional paid days off and recharge days
And much more, so do not hesitate to contact us
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