This is a unique opportunity to join the rapidly growing System Emulation team in the IP R&D Group at Cadence Design Systems. This is a tremendous opportunity to work with an experienced team focusing on development of high-performance IP related to protocols such as PCIe, CXL, UCIe, USB, DPHY and Ethernet PHYs. We are looking for a Lead Design Engineer who will be responsible for developing palladium verification platform for cadence PHY with Controller IPs and developing subsystem based FPGA prototyping design for all Cadence IPs. This is a hands on technical position. The candidate must have experience successfully integrating/designing/prototyping high speed IP in FPGA/Emulation Platform.