Lead Design Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

This is a unique opportunity to join the rapidly growing System Emulation team in the IP R&D Group at Cadence Design Systems. This is a tremendous opportunity to work with an experienced team focusing on development of high-performance IP related to protocols such as PCIe, CXL, UCIe, USB, DPHY and Ethernet PHYs. We are looking for a Lead Design Engineer who will be responsible for developing palladium verification platform for cadence PHY with Controller IPs and developing subsystem based FPGA prototyping design for all Cadence IPs. This is a hands on technical position.  The candidate must have experience successfully integrating/designing/prototyping high speed IP in FPGA/Emulation Platform.

Requirements:

• Should have 5+ years of experience in FPGA Prototyping/Emulation.
• Hand on experience on any FPGA/Emulation tool flow.
• Should have System Verilog/Verilog based coding.
• Experience in Writing C-based test cases.
• Experience in any high-speed IP (PCIE/USB/Ethernet/DPHY).
• Experience on system bus protocols USB3/PCIe, AXI, APB is desirable.
• Working experience on Cadence Simvision and Palladium/Protium Emulation
• Working knowledge of Python/TCL, Makefile scripting languages.
• Must have good communication skills.

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