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Drives development of products and technologies and has material responsibility for the success of that product/technology.
The responsibility entails performing pre silicon Physical Layer Electrical Validation infrastructure development as well as post silicon validation primarily on Cadence's High Speed SERDES Test chips, ie, activities involving (but not limited to) designing the hardware and software architecture required to test the test chips (be it the test PCBs, controlling FPGA platforms, Labview/python automation for controlling the HW etc), defining test plans for rigorously testing the compliance of the Test chips to the Physical Layer Electrical specifications, implementing these tests as planned, generating high quality test reports based on the test results etc.
Looking for 2-5 years of experience in Post-Silicon Validation related or hardware analog system level circuit design related activities
Experience and Technical Skills required (edit as per the requirement):
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