Lead Design Engineer

Cadence Design Systems

4.4

(53)

Bengaluru, India

Why you should apply for a job to Cadence Design Systems:

  • 4.4/5 in overall job satisfaction
  • 4.4/5 in supportive management
  • 87% say women are treated fairly and equally to men
  • 89% would recommend this company to other women
  • 87% say the CEO supports gender diversity
  • Ratings are based on anonymous reviews by Fairygodboss members.
  • Parental leave is available for both paternity and maternity
  • Flexible work options available
  • 88% of employees at Cadence say it is a great place to work compared to 57% of employees at a typical U.S.-based company.
  • #R47295

    Position summary

    configurations are clean as part of verification regressions, supporting customers in case of any issues with using the verification environment, and functional and code coverage.

    • As a part of delivery criteria, the engineer would need to provide Demosim testbench with standard test patterns that aid as a reference for customer for seamless integration of our IP's.

    • The engineer would be responsible to ensure that the design is in line with the technical and quality requirements set for the team - particularly with respect to functional and code coverage.

    • Participate in technical discussions and represent verification team in all the discussions with internal and external customers.

    • Review all technical deliverables from team members and guide team members to meet quality and the schedule.

    • Fully accountable for quality design verification as per the schedule.

    • Track the verification progress, identify potential risks, and mitigation plan.

    • Mentor and provide technical guidance to team working in the projects.

    • Contribute to verification process and methodology improvements to boost efficiency and productivity.

    Position Requirements:

    • Bachelor's/Master's degree in Electronics or Equivalent engineering stream

    • 5 to 8 years of Design verification experience with a large portion of the recent work experience on verification environment development.

    • Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.

    • Should have knowledge on all aspects of verification components & verification metrics.

    • System Verilog experience and experience with UVM based functional verification environment development is mandatory.

    • Prior RTL Design experience using Verilog is a must - so that the verification engineer is self-sufficient for most aspects of debugging.

    • HBM4 Protocol experience is highly desirable. Prior experience in functional verification and debugging of complex protocols is a must.

    • AXI3/4 experience is a desirable.

    • Prior experience in IP development teams would be an added advantage.

    Behavioral skills required:

    • Must possess strong written, verbal and presentation skills.

    • Good communication and interpersonal skills, demonstrate teamwork and collaboration skills.

    • Ability to establish a close working relationship with both customer peers and management.

    • Explore what's possible to get the job done, including creative use of unconventional solutions.

    • Work effectively across functions and geographies.

    • Push to raise the bar while always operating with integrity.

    We're doing work that matters. Help us solve what others can't.

    Why you should apply for a job to Cadence Design Systems:

  • 4.4/5 in overall job satisfaction
  • 4.4/5 in supportive management
  • 87% say women are treated fairly and equally to men
  • 89% would recommend this company to other women
  • 87% say the CEO supports gender diversity
  • Ratings are based on anonymous reviews by Fairygodboss members.
  • Parental leave is available for both paternity and maternity
  • Flexible work options available
  • 88% of employees at Cadence say it is a great place to work compared to 57% of employees at a typical U.S.-based company.