• OR PhD with 1 years of related experience
Experience and Technical Skills required
• 3-7 years relevant industry experience in EMIR analysis, PDN analysis with digital signoff tools and Digital Physical implementation as designer or methodology/flow expert.
• Strong background in Digital logic Design, CMOS logic Design, Power IR drop analysis, Circuit Design and Analysis, Digital and Behavioral simulation fundamentals related to IC and Package Design.
• Debugging of Low power and multiple power domain analysis for chip power integrity sign-off.
• Experience with 3DIC design and methodologies is a plus.
• Must have excellent debugging skills and ability to separate out the critical issues from trivial ones.
• Ability to solve interface level problems emanating from IC Implementation side and System analysis side.
• Ability to debug Timing and thermal issues in relation to IR and EM is a plus.
• Knowledge on TCL, Perl or Python scripting.
Behavioral skills required
• Must possess strong written, verbal and presentation skills.
• Ability to establish a close working relationship with both customer peers and management.
• Explore what's possible to get the job done, including creative use of unconventional solutions.
• Work effectively across functions and geographies.
• Push to raise the bar while always operating with integrity.
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