s, physical synthesis, floorplan, placement, STA signoff.
- Hands-on experience on running advanced process hierarchical, timing driven, SI prevention, low power place-and-route projects a big plus
- Familiar with logic synthesis tool (DC or Genus), P&R basic knowledge of ICC or EDI, STA (Tempus or PrimeTime-SI), Equivalence Checking (conformal-EC or Formality), UPF/CPF concept
- Knowledge of Linux and tcl is a must
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