• Candidate’s background should include a minimum of 5-10 years of experience in CMOS SerDes, ADC, or high-speed I/O IC design and development
• Working knowledge of a set of common SerDes standards and their electrical requirements
• Must have a thorough understanding of jitter and signal equalization techniques
• Design experience in most of the following SerDes circuit blocks: Driver; Receiver; Serializer; Deserializer; Phase Interpolator; Low jitter PLL; High Speed Clock Distribution; Bias and Bandgap; and Voltage Regulators
• Proficient Design Experience with ADC Designs and Architectures.
• Excellent problem solving skills, analog aptitude, good communication skills, and ability to work cooperatively in a team environment
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Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design™ strategy to deliver software, hardware, and IP that turn design concepts into reality.
Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial, and healthcare.