• Participate in the development of high-performance ASICs from specification to tape-out, including RTL,
synthesis, physical design, and timing closure • Maintain and enhance existing designs using Verilog/SystemVerilog
• Participate in the Implementation of new designs using Verilog/SystemVerilog
• Triage and troubleshoot failures down to the root cause
• Actively work with the verification team to deliver ASICs with high quality
• Actively work with the physical design team to resolve implementation and timing issues
• Develop tests and debug ASICs in the emulation
• Perform diagnostics and tests for ASICs in the lab
Education and Experience Required :
• Bachelor’s or Master’s degree in Electrical Engineering.
• 4+ years of ASIC design experience.
• Strong experience with Synthesis, Timing/Power Analysis.
Preferred Qualifications :
• Experience in design and integration of controllers for high speed interfaces like PCIE, Ethernet, DDR
• Experience with ARM protocols (AXI, CHI, APB, AHB) and exposure to ARM CPU's is a big plus.
- Experience with designing Hardware Accelerators is a big plus.
• Hands on experience in Design Verification and/or physical design is a plus.
• Familiarity with high performance and low power design techniques.
Knowledge and Skills :
• Excellent Verilog, System Verilog programming and debugging skills.
• Scripting experience (Python, Perl, TCL, shell programming).
• Proficient in synthesis constraints.
• Ability to write and debug test.
• Ability to debug system-wide issues.
• Good written and verbal communication skills.
• Collaborative and team-focused with the drive to learn and grow.
#WeAreCisco, where each person is unique, but we bring our talents to work as a team and make a difference.
Yes, we are the worldwide leader in IT, and our technology changes the way the world works, lives, plays and learns, but our edge comes from our people.