Sr. ASIC design verification engineer

Who You'll Work With

You will work with Cisco’s best-in-class switching solution team. Our team is responsible for driving integration of the Nexus systems and ACI with software, including OpenStack, Docker, and Open vSwitch, to help our customers build multi-tenant clouds.

What You'll Do

It used to be that high-speed packet forwarding was performed in dedicated ASIC designs. These days we are looking to make those ASICs more general and programmable. Cisco Common ASIC Group is looking for an expert Senior Verification Engineer to drive existing projects and engage in new development of our next generation switching systems.

As part of ASIC team, you will be developing the ASICs at the heart of each of these switch products. There are only a very few teams worldwide that implement such devices. Every time you access the Internet, chances are, your data's been through one of our switches.

Who You Are

You are a talented, motivated ASIC verification engineer to join the team and contribute to the verification of very complex ASICs. You will have a Design Verification background, hands-on experience in System Verilog and UVM methodology, with in-depth knowledge of C++, scripting, as well as ASIC design and verification flow.

You’ll be part of Cisco Common ASIC Group, focusing on developing various test benches and contributing to different aspects of verification infrastructure.

You will collaborate closely with the design team and the hardware team to verify the ASIC in simulation, in emulation and during ASIC bring up.

Responsibilities Include:

• Designing UVM/SystemVerilog testbenches.
• Defining new DV methodologies.
• Enhancing existing testbenches.
• End-to-end verification of various design blocks.
• Contributing to top level verification.
• Be a part of emulation testing efforts.
• Participate in the ASIC bring-up

Education and Experience Required:

• Bachelor’s or master’s degree in EE and CE.
• 5-10 years of ASIC Design Verification

Knowledge and Skills:

• Hands-on and deep understanding of System Verilog and UVM methodology
• Ability to construct testbenches including scoreboard, agents, sequencers, and monitors
• Ability to debug issues independently
• Proven Scripting experience (Python, Perl, TCL, shell programming) is a plus
• Proficient in functional coverage and constrained random DV environments
• Proficient in merging and analyzing code coverage data generated functional simulation
• Good written and verbal communication skills
• Very good hands-on knowledge on the latest high speed Ethernet protocol and packets
• Good working knowledge in C, C++ programming and debugging skills
• Collaborative and team-focused, with the drive to learn and grow

Why Cisco

#WeAreCisco, where each person is unique, but we bring our talents to work as a team and make a difference powering an inclusive future for all.

We embrace digital, and help our customers implement change in their digital businesses. Some may think we’re “old” (36 years strong) and only about hardware, but we’re also a software company. And a security company. We even invented an intuitive network that adapts, predicts, learns and protects. No other company can do what we do – you can’t put us in a box!

But “Digital Transformation” is an empty buzz phrase without a culture that allows for innovation, creativity, and yes, even failure (if you learn from it.)

Day to day, we focus on the give and take. We give our best, give our egos a break, and give of ourselves (because giving back is built into our DNA.) We take accountability, bold steps, and take difference to heart. Because without diversity of thought and a dedication to equality for all, there is no moving forward.

So, you have colorful hair? Don’t care. Tattoos? Show off your ink. Like polka dots? That’s cool. Pop culture geek? Many of us are. Passion for technology and world changing? Be you, with us!