ASIC RTL Engineer, Silicon

ification, FPGA and emulation platforms and SOC architecture.

• Knowledge of memory compression, fabric, coherence, cache, or DRAM.

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You will contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

• Define the block level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.).

• Perform RTL coding, function/performance simulation debug, and Lint/Clock domain crossing/Formal Verification/Unified Power Format checks.

• Participate in synthesis, timing/power closure, and FPGA/silicon bring-up.

• Participate in test plan and coverage analysis of the block and ASIC-level verification.

• Communicate and work with multi-disciplined and multi-site teams.