CPU Physical Design Implementation Engineer

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Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Science, a related field, or equivalent practical experience.

• 2 years of engineering experience.

• Experience in high-performance, low-power physical design and implementation techniques with industry standard synthesis and place and route tools.

• Experience in one or more sign-off convergence in Static Timing Analysis electrical checks and physical verification domains.

Preferred qualifications:

• 3 years of relevant industry experience on high-performance CPUs.
• Experience with computer architecture, logic design (RTL) and Knowledge of Verilog/SystemVerilog.
• Experience with Static Timing Analysis, power grid network delivery and power analysis tools.
• Working knowledge of CPU including critical iterations for timing and low power microarchitecture and implementation techniques for CPUs.
• Proficiency in programming and scripting languages such as Python, Tcl, and/or Perl.

About the job

As a CPU Physical Design Implementation Engineer, you'll perform physical design implementation for CPU designs. You will collaborate with Architects and Logic Designers to drive architectural feasibility studies, develop timing, power, and area design targets, and explore register transfer logic (RTL)/design tradeoffs for physical design closure. You'll also work with Verification and Software teams to understand and implement the design requirements for clocking and power management.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

• Develop Physical Design tools and flows for advanced CPU designs to achieve outstanding Power Performance Area (PPA).
• Collaborate with the RTL design teams on micro-architectural critical items for timing and power convergence.
• Manage block and hierarchical physical implementation and QoR (power, timing, area).

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.