Physical Design Engineering Manager, Silicon

Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Austin, TX, USA; Mountain View, CA, USA; San Diego, CA, USA.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, other related field, or equivalent practical experience

• 8 years of experience in ASIC physical design implementation and verification

• Experience managing a team of engineers

Preferred qualifications:

• Experience with leading one or more aspects of physical design
• Experience in IP integration (memories, IO’s, embedded processors, double data rate, networking fabrics, and Analog IP)
• Experience in extraction of design parameters, Quality of Results (QOR) metrics, and analyzing trends
• Knowledge of semiconductor device physics and transistor characteristics
• Scripting skills in Python, Tcl, or Perl

About the job

Google engineers develop the next-generation technologies that change how users connect, explore, and interact with information and one another. As a member of an extraordinarily creative, motivated and talented team, you develop new products that are used by millions of people. We need our engineers to be versatile and passionate to take on new problems as we continue to push technology forward. If you get excited about building new things and working across discipline lines, then our team might be your next career step.

As a Physical Design Engineering Manager, you will work on the physical implementation of ASICs using advanced technology nodes. In this role, you will lead a team that performs technical evaluations of vendors, process nodes, IP, and will provide recommendations. You will work with Architecture, Logic Design, and Design for Testing (DFT) teams to understand and implement their requirements. You'll drive block and sub-chip level physical implementation and closure. You will develop physical design methodologies, automation scripts, and write documentation.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

• Lead and manage a team of Physical Design Engineers developing ASICs in advanced nodes.
• Perform block level physical implementation steps including synthesis, floorplanning, place and route, power/clock distribution, congestion analysis, timing closure, EM/IR analysis, and formal verification.
• Work with Logic Designers to drive architectural feasibility studies, develop timing, power and area design goals, and explore RTL/design tradeoffs for physical design closure.
• Perform technical evaluations of vendors, process nodes, IP, and provide recommendations.
• Develop physical design methodologies and automation scripts for various implementation steps.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.