Semiconductor Wafer Fab Process Engineer

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• Communication and documentation skills.

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's Raxium display group has established a revolutionary semiconductor materials display technology that enables new functionality in display products, bringing to users a closer and more natural linkage between the digital and physical realms in applications such as augmented reality (AR) and light-field display. With start-up roots and a state-of-the-art compound semiconductor fab in Silicon Valley, Raxium is seeking to build upon its engineering team with an aim to disrupt next-generation display markets.

The US base salary range for this full-time position is $102,000-$150,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google .

Responsibilities

• Monitor, sustain, and support daily wafer fabrication processes encompassing areas of lithography, thin film, etch, clean, thermal, metrology/characterization and backside end of line processses.
• Ensure process reliability and consistency by providing technical support to operators, technicians, and other engineers.
• Review, propose, optimize, improve and implement various wafer fabrication processes for yield improvement, defectivity reduction, cycle time reduction, and general best practises of wafer handling.
• Enhance area process control plan and the process capability through implementation of best known manufacturing methods and statistical process control (SPC).
• Drive problem resolution process associated with the quality excursion in the fab area encompassing data analytics, methodical problem solving, failure analysis (FA), design of experiments (DOE), and mistake-proof.