#81655370459554502
e working with RTL design and integration teams on methodologies that improve team productivity and velocity.
Experience with Low Power Verification and power management flows.
Experience with Zero Delay, SDF, and Power Aware GLS at block and SOC level.
About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
Plan the verification of multimedia Intellectual Properties (IPs) at Subsystem and full chip level by fully understanding the design specification and interacting with architecture and design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using System Verilog and Universal Verification Methodology (UVM).
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.