Senior RTL IP/Component Design Engineer, Google Cloud

Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv-Yafo, Israel; Haifa, Israel.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering or equivalent practical experience.

• Experience in ASIC development with Verilog/SystemVerilog, VHDL or Chisel.

• Experience in 5 SOC cycles.

• Experience with ASIC design verification, synthesis, timing/power analysis, and DFT.

Preferred qualifications:

• Knowledge of high performance and low power design techniques.
• Knowledge of assertion-based formal verification.
• Knowledge of FPGA and emulation platforms.
• Knowledge of SOC architecture.
• Knowledge in one of these areas: arithmetic units, bus architectures, processor design, accelerators and/or memory hierarchies.
• Proficiency with a scripting language (e.g., python or perl).

About the job

In this role, you will contribute in all phases of complex application-specific integrated circuit (ASIC) designs from design specification to production. You will collaborate with members of architecture, software, verification, power, timing, synthesis and etc. to specify and deliver high quality SoC/RTL. You'll solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities

• Define the block level design document such as interface protocol, block diagram, transaction flow, pipeline and etc.
• Perform RTL development (e.g., coding and debug in Verilog, SystemVerilog, and VHDL), function/performance simulation debug and Lint/CDC/FV/UPF checks.
• Participate in synthesis, timing/power closure, and FPGA/silicon bring-up.
• Participate in test plan and coverage analysis of the block and SOC-level verification.
• Communicate and work with multi-disciplined and multi-site teams.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.