SoC Design for Testing Engineer, Google Cloud

Google

3.8

(162)

Tel Aviv-Yafo, Israel

Why you should apply for a job to Google:

  • 56% say women are treated fairly and equally to men
  • 77% say the CEO supports gender diversity
  • Ratings are based on anonymous reviews by Fairygodboss members.
  • Generous parental and caregiver leave along with fertility and growing family support.
  • Flexible work options that include a hybrid work model, four “work from anywhere” weeks, and remote work opportunities.
  • A chance to be a part of a variety of employee resource groups, community groups, and culture clubs.
  • #76951941036286662

    Position summary

    licon debug activities.

    About the job

    Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

    As a SoC DFT Engineer you will be responsible for defining, implementing and deploying advanced design for test (DFT) methodologies for highly digital or mixed-signal chips or IPs. You will define silicon test strategies, DFT architecture, and create DFT specifications for a CPU. You will design, insert and verify the DFT logic.You will prepare for post silicon and co-work/debug with test engineers. You will be responsible for reducing test cost, increasing production quality and enhancing yield.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

    Responsibilities

    • Develop DFT strategy and architecture (e.g., hierarchical DFT, Memory Built-In Self Test (MBIST), Automatic Test Pattern Generation (ATPG).
    • Complete all Test Design Rule Checks (TDRC) and Design changes to fix TDRC violations to achieve high-test quality.
    • Insert DFT logic, boundary scan, scan chains, DFT Compression, Logic BIST, TAP controller, Clock Control block, and other DFT IP blocks.
    • Insert and hook up MBIST logic including test collar around memories, MBIST controllers, eFuse logic, and connect to core and TAP interfaces.
    • Document DFT architecture, test sequences, and boot-up sequences associated with test pins.

    Why you should apply for a job to Google:

  • 56% say women are treated fairly and equally to men
  • 77% say the CEO supports gender diversity
  • Ratings are based on anonymous reviews by Fairygodboss members.
  • Generous parental and caregiver leave along with fertility and growing family support.
  • Flexible work options that include a hybrid work model, four “work from anywhere” weeks, and remote work opportunities.
  • A chance to be a part of a variety of employee resource groups, community groups, and culture clubs.