SoC Physical Design Manager

Minimum qualifications:

• Bachelor's degree in Electrical Engineering or equivalent practical experience.

• 15 years of experience in physical design.

• Experience managing a team of Engineers.

• Experience in synthesis, PnR, sign-off convergence, including Static Timing Analysis (STA) and sign-off optimizations.

Preferred qualifications:

• Experience in full-chip floor planning, place and route, IP integration.

• Experience in low power design Implementation including UPF, multi-voltage domains, power gating.

• Experience with ASIC design flows and methodology of Physical design.

• Understanding of circuit design, device physics and deep sub micron technology.

About the job

Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

Pulling on your technical and leadership expertise, you lead end-to-end research projects in multiple areas of expertise across data center facilities and manage a team of direct reports working on equipment installation, troubleshooting and debugging.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

• Develop all aspects of ASIC RTL2GDS implementation for high Power Performance Area (PPA) designs.
• Lead and manage physical implementation engineers to deliver SoC full-chip integration.
• Work with cross-functional teams to deliver best quality of results.
• Develop design area, power and performance targets, and explore RTL/design tradeoffs for physical design closure.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.