IBM LOGIC DESIGN ENGINEER - Cache

rticipate in silicon bring-up and validation of the hardware

• Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums.
• Estimate the overall effort to develop the feature.
• Estimate silicon area and wire usage for the feature.
  #ISDL_ESD2Q24, #ISAISDLESD24

#ISAISDLESD24

Required Technical and Professional Expertise

• 4 to 8 years of relevant experience

• At least 1 generation of processor L2 cache or LLC design delivery leadership.

• Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP.

• Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations.

• Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory.

• Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

Preferred Technical and Professional Expertise

• None