RF-SoC User Experience Group (RFUE) is looking for individuals to develop/enhance supplement RF/SoC PDK libraries. Candidates should have experience working with EDA software tools such as Cadence Virtuoso, Mentor Calibre, Synopsys ICV, Ansys HFSS. Job requires expertise in electromagnetic solvers and extraction flows and methodologies.
Additional responsibilities include:
- Create flows/scripts to analyze and test design methodologies, with respect to RC and device-level parasitic extraction.
- Create and execute QA test cases and regression suites.
- Apply design methodologies to help execute projects effectively and successfully with high quality.
The candidate should exhibit the following behavioral traits:
- Collaborator with leadership, communication, and influencing skills.
- Written, presentation, and communication skills
Relocation assistance will not be offered for internal candidates
Master of Science Degree in Computer Engineering with a minimum of 6 years of working experience OR a PhD in Computer Engineering with a minimum of 3 years of working experience in the following:
- Creation and Debug of P-cell (parameterized cell) in Cadence Virtuoso environment.
- Cadence Skill language, Techfiles and Automation.
- IC RF/Analog/Digital Design and Layout environment.
- EDA IC design flows and related Layout methodologies.
- Programming languages: Unix Shell, Perl, Python, Skill, Tcl, P-cell coding, Ocean scripting.
- CMOS Design (front-to-back), ASIC Design and RF/Analog flows. Runset development/support.
- Cadence DFII environment such as Schematic Composer and Virtuoso Layout Editor.
- Debugging Parasitic Extraction and Fill flows across multiple technologies.
Experience working in Process Design Kit development environment
- Minimum of 3 years of external foundry experience.
- Minimum of 5 years of experience with industry based (CAD) layout
- Experience with Cadence Skill P-cell creation and debugging, CDF, callbacks.
- Expertise with Cadence Skill programming and Automation.
- Experience with ICV/Calibre/PVS for DRC/LVS and debug of such runsets.
- Experience with parasitic extraction, fill and RV flows in newer CMOS (finfet) technologies.
- Experience using Cadence QRC, Mentor Calibre, Synopsys StarRC.
- Experience with RTL2GDS flows using Cadence and Synopsys tools.
- Experience working on INTEL and/or other foundry Process Design Kits
Inside this Business Group
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moores Law to bring smart, connected devices to every person on Earth
US, California, Santa Clara;US, Oregon, Hillsboro
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance....