Develops and tests Engineering Design Automation tools, creates flows/scripts to analyze and test design methodologies. Specifies materials, equipment and supplies required for completion of projects. Evaluates vendor practical capabilities to provide required products or services. Responsible for designing, deploying and testing efficiency of tools to utilize in achieving design goals and collaborating with design teams on methodology development. Design Automation Engineers are advocates of applying design methodologies to help execute projects effectively and successfully with high quality.
RF-SoC User Experience Group (RFUE) is looking for individuals to develop/enhance supplement RF/SoC PDK libraries. Candidates should have experience working with industry standard EDA reliability tools. Expertise in reliability verification flows and methodologies. Create flows/scripts to analyze and test design methodologies around RV flows. Create and execute QA test cases and regression suites. Apply design methodologies to help execute projects effectively with high quality.
The ideal candidate should exhibit the following behavioral traits:
- Leadership, communication, and influencing skills.
- Written, presentation, and communication skills are necessary.
Leading cross-functional teams to develop robust qualification strategies.
Master of Science Degree in Computer Engineering with a minimum of 6 years of working experience OR a PhD in Computer Engineering with a minimum of 3 years of working experience in the following:
- Semiconductor engineering in the IC Design flows with exposure to different design/verification/reliability flows from EDA vendors.
- Analog/RF fundamentals, aging models.
- IC RF/Analog/Digital Design and layout environment with PDK collateral knowledge.
- EDA IC design flows, Simulation Environment and layout methodologies.
- Programming languages: Unix Shell, Perl, Python, Skill, Tcl, Pcell coding, Ocean scripting
- CMOS Design (front-to-back), ASIC Design and RF/Analog flows.
- Cadence Virtuoso environment, Schematic Composer and Virtuoso Layout Editor.
- Cadence SKILL scripting, P-cell creation and automation.
Debugging Extraction, Fill and Reliability verification flows across multiple technologies
- Minimum of 3 years of external foundry experience.
- Minimum of 5 years of experience with industry based (CAD) layout
- Experience with 2D and 3D field solvers, Voltus-Fi, Totem, PERC, Redhawk tools.
- Experience with ICV/Calibre for DRC/LVS and debug of such runsets.
- Expertise with Reliability flows in newer CMOS (finfet) technologies.
- Expertise with Cadence Skill programming and Automation.
- Experience with ICV/Calibre/PVS for DRC/LVS and debug of such runsets
Inside this Business Group
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moores Law to bring smart, connected devices to every person on Earth
US, California, Santa Clara;US, Oregon, Hillsboro
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance....