Design Verification Engineer
Santa Clara, CA
Come and join us! Intel is seeking highly qualified candidates to join the BXD (Barefoot Switching Division) in our Data Center Group (DCG) as a Design Verification Engineer! We're part of the Connectivity Group (CG) inside Intel's DCG, and we're looking for motivated, passionate and talented engineers to join our Dv team. We're a strong, vibrant cross-site team which helps drive Intel's programmable switching technology and products to position Tofino as the switching platform of choice and for the Cloud and Data Center network deployments.
In this role, you will be responsible for defining and implementing verification methodology. This is a great opportunity to join the front-end design team in a pre-Si verification role, early in the product lifecycle, as we enter the technology readiness (TR) phase, then move into design and execution
Responsibilities will include, but are not limited to:
- Developing verification infrastructure from ground up.
- Work with Architecture and RTL groups to provide solutions for complex technical challenges.
- Responsible for validating RTL from the uArch definition
- Responsible for the coverage closure of the block(s)
- Require to work with system and software teams
Responsible for providing complete test plan documentation for the block
The ideal candidate will have the following skills in addition to the qualifications listed below.
- Must be a team player, with a demonstrated expertise to technically influence others.
- Strong problem-solving skills.
Excellent verbal and written communication skills.
In this position you will gain invaluable experience which will allow growth and expanded opportunities within this business group as well as future possible opportunities with other business groups within Intel.
The Data Center Group (DCG) drives new products technologies from high-end co-processors for supercomputers to low-energy systems for enterprise and the cloud, as well as solutions for big data and intelligent devices. The group is a worldwide organization that develops the products and technologies that power 9 of every 10 servers sold worldwide.
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Required Qualifications:
- Bachelor's degree in Electrical Engineering or Computer Science and 3+ years industry experience.
3+ years of experience implementing verification methodology and verifying in any of the following key areas of our next generation ASIC:
- Serdes, PCIE protocols, MAC protocols
- Packet Classification (Layer 2 classification experience is big plus)
- Algorithmic Search Units
3+ years of experience in C/C++ programming
3+ years of experience in System Verilog programming
Additional Preferred Qualifications:
- 3+ years of experience with Full Chip Bring up
- 3+ years of experience with Emulation
- Masters of PhD in Electrical Engineering or Computer Science and 3+ years industry experience
Inside this Business Group
The Data Center Group (DCG) is at the heart of Intels transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologiesspanning software, processors, storage, I/O, and networking solutionsthat fuel cloud, communications, enterprise, and government data centers around the world.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance....