IP Logic Design engineer
Santa Clara, CA
Performs logic design, Register Transfer Level (RTL) coding, and simulation to generate cell libraries, functional units, and subsystems for inclusion in full chip designs.
Participates in the development of Architecture and Microarchitecture specifications for the Logic components.
Provides IP integration support to SoC customers and represents RTL team.
Suitable candidate will also have:
- Strong communication skills and a good team player.
Experienced in working with multi-site projects.
Join Intel's newly formed Configurable Fabric Group (CFG) where we develop the core fabric and IP technology to push the boundaries of what's possible in System-On-Chip (SoC) architecture and design.
Suitable candidate will have a minimum Bachelors Degrees in Computer Engineering or Electrical Engineering with"
- 5+ years in RTL design
- Experience in microarchitecture
Experience with UVM and scripting
Inside this Business Group
The Silicon Engineering Group is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs that power Intels leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance....