Product Development Engineer IO/PLL
Santa Clara, CA
The Data Center Manufacturing Engineering group is looking for a motivated engineer to join the team to work in the highly challenging environment of product development across Intel's XEON product families. The product development engineers in this team work on Architecture definitions, Circuit and Logic Design and Development recommendation for DFT implementations, Verification and Validation model development, Functional and Structural test content development with teams worldwide. This team is responsible to maintain Intel's design and manufacturing quality of baseline product to the external world. This engineering team is specifically responsible for ensuring the testability and manufacturability of high speed serial I/O and PLL from architectural design through to production ramp for server CPUs. This engineering team is also responsible for ensuring server CPUs' HSIO meeting the electrical parametric specifications before product qualification.
Responsibilities of the engineers may include:
DFT Design (Design for Test)
Pre-Silicon validation of Analog test content at IP and full chip level including test writing.
Test content generation of patterns to support HVM testers as well as Bench DV.
Silicon debug to identify functional and DFT related bugs and silicon characterization to validate IP.
Support platform and system level validation teams to identify and close silicon issues.
Analysis and disposition of early customer returns to drive understanding of design marginalities or develop test content to screen these units where needed. To work with Sort and Class teams to deliver high quality analog test content and support improving product health indicators.
BS Degree in Electrical Engineering, Computer Engineering, Computer Science or a closely related field plus 5 years of experience -OR- a MS Degree plus 3 years of experience.
Additional preferred qualifications include the following:
- Knowledge of PLL, IO protocols, specs, DFT architectures, and design (PCI Express, SATA, USB3, DDR, WIO etc.) is highly desired.
- Development, evaluation and validation of analog and DFT circuits including concepts such as jitter, margining, squelch, equalization.
- Strong software programming skills in Python, C, or C++
- Knowledgeable in high volume manufacturing flows and statistical data analysis
- Experience driving tester to support debug and characterization of silicon
- RTL, GLS and VTPsim test writing, simulation and validation experience.
- Silicon debug and characterization of new products including working with platform and system level validation teams to identify and close silicon issues.
- Experience in using oscilloscopes, J-bert, spectrum and Logic analyzer.
- Understanding of circuits and logic design methodology.
- Understanding of device physics.
Inside this Business Group
The Infrastructure and Platform Solutions Group (IPSG) builds the silicon and platform infrastructure for Intel's silicon design teams. IPSG is comprised of a reusable pool of infrastructure IP blocks, design enabling services such as tools and automation, and a best-in-class post silicon ecosystem that ramps quickly to high volume manufacturing and validation. Our primary mission is to protect Intel's brand by providing the infrastructure necessary to enable all of Intel's products to hit the market on a dependable and predictable cadence.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance....