Staff Digital Verification Engineer (Senior Level)

of exotic new technologies and drives advancements in the sciences. One of our most challenging new fields is Transformational Computing, which combines the unique properties of superconductivity and quantum mechanics to develop radical new energy-efficient computing systems. Our team is chartered with providing the skills to transform computing beyond Moore's Law, advancing development of computer architectures, processing/memory subsystems, and large scale high performance computing systems. You will be part of a team alongside a broad array of scientists and engineers working to make these processing solutions a reality.

We are seeking a digital verification engineer to support these effort through verification of RTL designs targeted for FPGA and standard cell library ASIC implementation . Must be proficient in HDL (VHDL/Verilog) and HVL (SystemVerilog). Experience with SystemVerilog Assertions (SVA) and Universal Verification Methodology (UVM) is required. Successful candidates will have familiarity with a coverage-driven verification methodology from planning through closure as well as knowledge of industry standard interfaces. Experience with object oriented programming languages and concepts is also required. Must have strong written and oral communication skills.

This work will be done onsite at either our Baltimore, MD; or Beavercreek, OH Facilities.

Basic Qualifications Staff Digital Verification Engineer:

• Bachelor's degree in electrical engineering or STEM related discipline with 14 years of relevant experience in Verilog and System Verilog; OR 12 years with a Masters Degree; OR 10 years with PhD
• Experience and understanding necessary to develop comprehensive verification plans
• Experience with SystemVerilog Assertions (SVA)
• Knowledge of Universal Verification Methodology (UVM)
• Experience with scripting languages (Bash, Perl, Python, Tcl)
• Familiarity with a coverage driven verification methodology from planning through closure
• Experience with object oriented programming languages and concepts
• Must be a US Citizen and must be able to obtain and maintain a Top Secret/SCI security clearance.

Preferred Experience in any of these areas:

• Advanced Degree either MS or PhD
• Active Full Top Secret/SCI security clearance with Polygraph.
• Advanced experience in HDL (VHDL/Verilog) and SystemVerilog (HVL).
• Experience with Mentor Graphics and/or Cadence Verification tools.
• ASIC/FPGA Design experience.

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Salary Range: $161,000 - $265,700

Employees may be eligible for a discretionary bonus in addition to base pay. Annual bonuses are designed to reward individual contributions as well as allow employees to share in company results. Employees in Vice President or Director positions may be eligible for Long Term Incentives. In addition, Northrop Grumman provides a variety of benefits including health insurance coverage, life and disability insurance, savings plan, Company paid holidays and paid time off (PTO) for vacation and/or personal business.
Northrop Grumman is committed to hiring and retaining a diverse workforce. We are proud to be an Equal Opportunity/Affirmative Action Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class. For our complete EEO/AA and Pay Transparency statement, please visit http://www.northropgrumman.com/EEO . https://U.S. Citizenship is required for most positions.