#450483-en 1
ally requires minimum of 5+ years of experience in Physical Design with mainstream P&R tools
Should be able to understand and communicate with foundry partners and internal teams on the exact issues and requirements.
Have basic knowledge of the physical design rules (mainly the routing layers) from the foundry.
Understand how to analyze routing issues and DRC violations.
Hands on experience in Physical Design (floorplan, placement, CTS and routing).
Hands-on experience with commercial place & route tools like Synopsys-ICC2/FC, Cadence-lnnovus or Aprisa is a must.
Tapeout experience is a plus.
TCL, Perl or Python scripting is a plus.
Strong verbal and written communication skills; good presentation skills
Good problem solving and debugging skills
Proficiency in Korean and English is required
Bachelors in Electronics and Communication (E&C) or Electrical or Telecom Engineering
Masters in VLSI or Microelectronics is a plus.
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