AE Junior in System Verification

hops covering the Functional Verification Platforms and over time mature into a strong team member and become a key contributor, leading projects and initiatives. The position will include travel to customer sites and involve significant interaction with customers.

Responsibilities:

Provide direct technical pre-sales support for Cadence Verification products, in the context of a solid technical understanding of the complete verification flow.

• Manage strategic customer evaluations/benchmarks of Cadence verification solutions to establish technology differentiation and assert Cadence competitive advantages

• Assist customers in adopting Cadence technology by providing Verification methodology and tool knowledge to design and verification engineers, validated through successful implementation

• Drive best practices and lessons learned from delivering training, benchmarks and customer interactions back into product development and Cadence field engineers; build understanding of the customer's needs and of the competition's technology and sales strategies.

• Perform methodology assessments, improve existing design / verification methodologies and develop new ones that leverage Cadence technology and services.

• Take part in technical campaigns to enable our customers to adopt existing and new technologies and solutions.

Requirements:

The candidate should have:

• Master Eng in Electronic / Micro-Electronic Engineering or equivalent

• Around 1 year of experience in hands-on Verification.

• Experience of Hardware Design and Verification languages including Verilog, VHDL System Verilog and UVM

• This job position requires a good understanding of:

  • Common verification flows and methodologies such as UVM, Coverage-Driven Verification, Assertion-based Verification, Low-Power Verification and Software Driven Verification
  • Experience and knowledge of protocols like AMBA, Ethernet, USB, PCIe, MIPI (Not require all)
  • Experience with Unix / Linux environment including scripting languages

• Of advantage would be:

  • Experience in Formal property checking (PSL or SVA)
  • Knowledge in one or more of the following Languages in the context of Design & Verification: UPF, C / C++ / System-C / TLM / Specman e
  • Familiar with the full SoC design flow

• Excellent problem-solving skills and Good Communication skills are a must

• Team orientation, mature work attitude, and good judgment under pressure

• Ability to travel in Southern Europe and world-wide

• Fluent in English and in Italian, speaking and writing is essential; French language knowledge is of advantage.

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