AVIP Hardware / Software Engineer

nication protocols, used in both emulation and simulation environments. Our products span SystemVerilog/Verilog models, C/C++ and SystemC software components, and full SV-UVM verification environments. Development includes both protocol-level modeling and system-level architecture.

We're looking for a talented and driven HW/SW Engineer to join the AVIP team and contribute to develop, support and maintain our emulation solutions for communication protocols. This role offers full product ownership - from initial definition, through hands-on development, integration, and delivery to customers - while working closely with multiple groups across Cadence - Development, Marketing, Field, etc. and with our customers.

Requirements:

• BSc in Electronics/Electrical Engineering from a leading institute.

• 2-4 years of hands-on HW/SW development experience in an industrial setting.

• Knowledge and experience in Verilog/SystemVerilog.

• Well versed in object-oriented design, SystemC/C/C++ programming experience is a plus.

• Good communication skills, excellent inter-personal skills, motivated individual.

• Strong analytical skills, able to solve complex problems independently.

Advantages:

• Emulation experience on Palladium.

• Familiarity with different communication protocols.

• Familiarity with UVM methodologies.

• Familiarity with Compilation flows and scripting.

• Experience with EDA software.

• Fluent in English.

• Good sense of humor.

We're doing work that matters. Help us solve what others can't.

We're doing work that matters. Help us solve what others can't.