Design Engineer II

Engineering Director**

Job Overview:

The Cadence Computer Systems Group (CSG) develops and licenses IP for system designs. This includes CPUs and high-performance DSPs, DDR and IO controllers, hardware accelerators, and subsystems. Our IP designs are used by most of the top semiconductor vendors today, and our customers are shipping billions of chips annually using our components.

The CSG Central Applications Engineering team seeks an experienced and talented SoC design engineer to join a new team for CSG systems. In this role, you will be responsible for developing and validating reference systems for Computer Vision, Machine Learning, Radar, Automotive, and other high-performance applications.

This is a technically rewarding role with high visibility within the organization. The team is responsible for supporting customers of CSG subsystems. The group will also implement reference designs on emulation systems and support applications for product demonstrations.

This role requires prior experience in RTL design or verification. You will work closely with compute and interface IP development engineering and build designs to demonstrate the capabilities of CSG subsystems and components.

Responsibilities:

• Develop, implement, and debug SoC reference systems.

• Integrate compute, memory and interface IP in system designs.

• Analyse IP products and implementation flows.

• Identify gaps and work with development teams to improve products.

• Develop collateral, and training material for CSG system customers.

• Identify and implement best practices in hardware design, testing, and validation to improve efficiency and reliability.

• Stay up to date with latest industry trends, technologies, and design methodologies, and incorporate them into team's workflows.

Requirements:

• BS in Electronic Engineering/Computer Science with 3+ years work experience, or MSc in EE/C.

• Must have experience in RTL design, including micro-architecture definition of digital portions of IP blocks, or verification. Demonstrated experience in any of the following areas:

  • Design of digital circuits and components using Verilog/System Verilog
  • Debugging in digital simulation environment
  • Multi-clock domain designs
  • Logic synthesis
  • FPGA implementation

• Working knowledge of UNIX/Linux, Shells, programming and scripting.

• Experience with EDA tools like Cadence and Synopsys for design simulation and verification.

• Working knowledge of leading protocols (i.e. PCIe, CXL, AMBA, Ethernet, USB, ...)

• Ability to use UVM TB

• Excellent communication (Fluency in English)

• Must be legally eligible to work in Poland.

Additional Information:

Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.
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