#R52982
Solid understanding of Verilog/SystemVerilog
ASIC Fundamentals:
Familiarity with design flows including RTL, simulation, synthesis,and timing
Scripting Skills:
Working proficiency in Python, Perl, TCL, or Shell scripting
Tool Aptitude:
Quick learner with ability to master new EDA tools and methodologies
Bonus Points:
✓ Exposure to Power Flow concepts (UPF/CPF)
✓ Experience with DFT, CDC, LEC, or formal verification tools
✓ Knowledge of UCIE (Die-to-Die) interfaces or analog design flows
✓ Familiarity with version control systems (Git, SVN)
✓ Prior internships or academic projects in VLSI/ASIC domain
Technical Skills
Advanced IP integration techniques
Comprehensive QA methodologies
Synthesis & timing analysis
AI/ML in chip design (Agentic AI)
Process automation & scripting
Front-end & back-end design flows
Professional Skills
Stakeholder management
Cross-functional collaboration
Technical documentation
Problem-solving at scale
Quality assurance mindset
Global team dynamics
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