Design Engineering Architect

pment and execution, and collaboration with other functional teams to achieve functional and performance closure.

Candidate Must Have Thorough Understanding Of

• Mixed-signal circuit design fundamentals

• Basic signal processing concepts

• High-Speed Analog/Mixed-Signal circuit design and verification flows

• Cadence analog design environment

Familiarity with The Following Items Is a Plus

• Serial link design techniques

• Serial link receiver analog frontend (high bandwidth termination, CTLE, VGA

• Data converter (ADCs and/or DACs) and/or clock synthesis and recovery (PLLs, DLLs, CDRs) techniques

• Hardware description languages such as SystemVerilog or VerilogA for functional model development

• MATLAB, Python or C to facilitate architecture development

• Scripting languages such as Perl or Python for automation

• Silicon validation testing knowledge and experience

Other Requirements

• Excellent verbal and written communication skills

• PhD EE degree with 8+ or MS with 10+ years of relevant industry experience

We're doing work that matters. Help us solve what others can't.

The annual salary range for California is $178,500 to $331,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
We're doing work that matters. Help us solve what others can't.